MSPA1000: Mixed Signal Platform Architecture

LinearChip has developed a new ASSP design platform called the MSPA1000 (Mixed Signal Platform Architecture). From Motor Control to LED lighting, Automotive to Military, the MSPA1000 platform has the price point and performance required to meet the needs of thousands of designs in development today.

Targeting low cost, mixed signal applications requiring 8 to 32 bit performance, LinearChip has put together a large list of IP and created a solid platform to help meet your future needs.


Beyond Semi BA22, silicon proven, 32-Bit ARM™ class processor:

  • Extremely low gate count options (8-Bit uP footprint)MSPA1000
  • Excellent code density
  • Hardware implemented DSP instructions available
  • Custom instructions available
  • Embedded DEBUG controller
  • Fully synthesizable RTL available
  • Software design and support available

Digital IP and Services:

  • Standard and custom IP blocks available
  • Front end Digital design services which include Mixed Mode RTL & Test Bench design, Synthesis & STA Constraint generation, etc.
  • Backend Digital design services which include place and route test insertion, power analysis and partitioning, floorplanning, GDSII handoff etc.

Analog IP and Services:

  • Large list of analog IP blocks available for immediate use
  • A2D, D2A, OpAmp, DiffAmp, VGA, LNA, FET DRV, R,L,C Trim, Bandgap, LDO, Boost, Buck, PLLs, etc.
  • Custom HV, LP analog blocks, IOs and IP design available


  • IBIS, SPICE, etc.


  • Hall, Accelerometer, Tilt, Relay and many others through our 3rd party partners


  • Wafer, KGD, WLCSP, QFN, QFP, BGA, Flip Chip, Ceramics (DIP, LCC) etc.


  • Solid list of supported tools and software from industry leading companies
  • Processor: Compiler, Assembler, Linker, Simulator, Debugger and selection of OS

Test Insertion and Mixed signal test:

  • Embedded self test methodologies
  • In house experts in mixed signal test development and testing strategy

Emulation and prototype:

  • FPGA based platform for digital ASIC development and interconnect to proven Analog IP available
  • MPW (multi-project-wafer) shuttle programs for quick turn, low cost proof of concept silicon


  • Low to high volume. MPW (10’s), MLM (multi-layer-mask, 100’s of K) and full mask (high volume)
  • Complete and experienced production supply chain: Test, Packaging, Product Qualification and Yield Enhancement through close collaboration with our suppliers.